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Engineering Specification
Engineering Specification Type 15.0 XGA Color TFT/LCD Module Model Name:N150X4-L01
Document Control Number : OEM N150X4-L01-01
Note:Specification is subject to change without notice. Consequently it is better to contact to International Display Technology before proceeding with the design of your product incorporating this module.
Sales Support International Display Technology
(C) Copyright International Display Technology 2002 All Rights reserved. February 06,2003 OEM N150X4-L01-01 1/29
Engineering Specification
i Contents
i Contents ii Record of Revision 1.0 Handling Precautions 2.0 General Description 2.1 Characteristics 2.2 Functional Block Diagram 3.0 Absolute Maximum Ratings 4.0 Optical Characteristics 5.0 Signal Interface 5.1 Connectors 5.2 Interface Signal Connector 5.3 Interface Signal Description 5.3.1 E-EDUD 5.4 Interface Signal Electrical Characteristics 5.4.1 Signal Electrical Characteristics for LVDS Receiver 5.4.2 LVDS Receiver Internal Circuit 5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection 5.5 Signal for Lamp connector 6.0 Pixel format image 7.0 Parameter guide line for CFL Inverter 8.0 Interface Timings 8.1 Timing Characteristics 8.2 Timing Definition 9.0 Power Consumption 10.0 Power ON/OFF Sequence 11.0 Mechanical Characteristics 12.0 National Test Lab Requirement
(C) Copyright International Display Technology 2002 All Rights reserved. February 06,2003 OEM N150X4-L01-01 2/29
Engineering Specification
ii Record of Revision
Date February 06,2003 Document Revision OEM N150X4-L01-01 Page All Summary First Edition for customer. Based on Internal Spec."N150X4-IPI-01"
(C) Copyright International Display Technology 2002 All Rights reserved. February 06,2003 OEM N150X4-L01-01 3/29
Engineering Specification
1.0 Handling Precautions
O If any signals or power lines deviate from the power on/off sequence, it may cause shorten the life of the LCD module. O The LCD panel and the CFL are made of glass and may break or crack if dropped on a hard surface, so please handle them with care. O CMOS ICs are included in the LCD panel. They should be handled with care, to prevent electrostatic discharge. O Do not press the reflector sheet at the LCD module to any directions. O Do not stick the adhesive tape on the reflector sheet at the back of the LCD module. O Please handle with care when mount in the system cover. Mechanical damage for lamp cable/lamp connector may cause safety problems. O Small amount of materials having no flammability grade is used in the LCD module. The LCD module should be supplied by power complied with requirements of Limited Power Source (2.5, IEC60950 or UL60950), or be applied exemption conditions of flammability requirements (4.7.3.4, IEC60950 or UL60950) in an end product. O The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit (2.4, IEC60950 or UL60950). O The fluorescent lamp in the liquid crystal display(LCD) contains mercury. Do not put it in trash that is disposed of in landfills. Dispose of it as required by local ordinances or regulations. O Never apply detergent or other liquid directly to the screen. O Wipe off water drop immediately. Long contact with water may cause discoloration or spots. O When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or abrasives. O Do not touch the front screen surface in your system, even bezel. O Gently wipe the covers and the screen with a soft cloth.
O
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by International Display Technology for any infringements of patents or other right of the third partied which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of International Display Technology or others. The information contained herein may be changed without prior notice. It is therefore advisable to contact International Display Technology before proceeding with the design of equipment incorporating this product.
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(C) Copyright International Display Technology 2002 All Rights reserved. February 06,2003 OEM N150X4-L01-01 4/29
Engineering Specification
2.0 General Description
This specification applies to the Type 15.0 Color TFT/LCD Module 'N150X4-L01'. This module is designed for a display unit of a notebook style personal computer. The screen format and electrical interface are intended to support the XGA (1024(H) x 768(V)) screen. Support color is native 262k colors ( RGB 6-bit data driver ). All input signals are LVDS(Low Voltage Differential Signaling) interface compatible. This module does not contain an inverter card for backlight.
(C) Copyright International Display Technology 2002 All Rights reserved. February 06,2003 OEM N150X4-L01-01 5/29
Engineering Specification
2.1 Characteristics
The following items are characteristics summary on the table under 25 degree C condition: CHARACTERISTICS ITEMS Screen Diagonal [cm] Active Area [mm] Pixels H x V [pixels] Pixel Pitch [mm] Pixel Arrangement Display Mode White Luminance [cd/m2] Contrast Ratio Viewing Angle Color Chromaticity Surface Treatment Optical Rise + Fall Time Nominal Input Voltage [VDD] Logic Power Consumption [watt] CFL Power Consumption [watt] Weight [grams] Physical Size [mm] Electrical Interface Support Color Temperature Range [deg. C] CFL cable length SPECIFICATIONS 38 304.128(H) x 228.096(V) 1024(x3) x 768 0.297(per one triad) x 0.297 R.G.B. Vertical Stripe Normally Black 215 Typ. (Screen Center, ICFL = 6.5mA) 400 : 1 Typ. 300:1 Min CR>=10:1 H: +/-85 deg., V:+/-85 deg. Typ. CR>=100:1 H: +/-40 deg., V:+/-40 deg. Typ. x:0.313 , y:0.329 Anti-Glare,AG160 60msec Typ.; +3.3 V 1.6 Typ. (All White Pattern), 2.2 Max (worst pattern) 4.1Typ.(@ICFL=6.5mA) 585 Max. 317.3(W) x 242.0(H) x 6.2(D) Typ. 4 pairs Single LVDS(Single) Native 262K colors ( RGB 6-bit data driver ) 0 to +50 (Operating) -20 to +60 (Storage, Shipping) 60 mm 120ms Max. (@25degC)
(C) Copyright International Display Technology 2002 All Rights reserved. February 06,2003 OEM N150X4-L01-01 6/29
Engineering Specification
2.2 Functional Block Diagram
The following diagram shows the functional block of the Type 15.0 Color TFT/LCD Module.
Signal Connector
FI-XB30SL-HF10
X-Driver
<4 pairs LVDS>
RxIN0 RxIN1 RxIN2 RxCLKIN
VEEDID CLCEEDID DataEEDID
LCD DRIVE CARD
LCD
Controller
TFT ARRAY/CELL 1024(R/G/B) x 768
EEDID Chip
DC-DC Converter Ref circuit
Y-Driver
VDD GND
Backlight Unit
CCFL Connector
BHSR-02VS-1 (JST)
CCFL High Voltate CCFL Low Voltage
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Engineering Specification
3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as follows : Item Supply Voltage Input Voltage of Signal Lamp Ignition Voltage CFL Current CFL Peak Inrush Current Operating Temperature Operating Relative Humidity Storage Temperature Storage Relative Humidity Vibration Shock Note :
1.
Symbol VDD Other Inputs Vinv ICFL ICFLP TOP HOP TST HST
Min -0.3 -0.3 0 8 -20 5
Max +4.0 VDD+0.3 2,000 7 20mA / 50ms +50 95 +60 95 1.5 50 10-200 18
Unit V V Vrms mArms
Conditions
A single pulse deg.C %RH deg.C %RH G G Hz ms Rectangle wave (Note 1) (Note 1) (Note 1) (Note 1)
Maximum Wet-Bulb should be 39 degree C and No condensation.
(C) Copyright International Display Technology 2002 All Rights reserved. February 06,2003 OEM N150X4-L01-01 8/29
Engineering Specification
4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 degree C condition: Item Viewing Angle (Degrees) K:Contrast Ratio Contrast ratio Response Time (ms) Color Chromaticity (CIE) Rising + Falling Red Red Green Green Blue Blue White White White Luminance (cd/m ) ICFL 6.0 mA
2
Conditions Horizontal KP10 Vertical KP10 (Right) (Left) (Upper) (Lower)
Specification Typ. 85 85 85 85 400 60 0.313 0.329 200Typ. Center Note 120 Max. 160Min Center
x y x y x y x y
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Engineering Specification
5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module. These connectors are capable of accommodating the following signals and will be following components. Connector Name / Designation Manufacturer Type / Part Number Mating Receptacle/Part Number For Signal Connector JAE FI-XB30SL-HF10 FI-X30M, FI-X30C2L
Connector Name / Designation Manufacturer Type / Part Number Mating Type / Part Number
For Lamp Connector JST BHSR-02VS-1 SM02B-BHSS-1
(C) Copyright International Display Technology 2002 All Rights reserved. February 06,2003 OEM N150X4-L01-01 10/29
Engineering Specification
5.2 Interface Signal Connector
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Signal Name GND VDD VDD VEDID (Note 2, 3) Reserved (Note 1) CLKEEDID (Note 2, 4) DataEEDID (Note 2, 4) RxIN0RxIN0+ GND RxIN1RxIN1+ GND RxIN2Pin # 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Signal Name GND RxCLKINRxCLKIN+ GND NC NC GND NC NC GND NC NC GND NC
15 RxIN2+ 30 NC Note : 1. 'Reserved' pins are not allowed to connect any other line. 2. This LCD Module complies with "VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA STANDARD Release A, Revision 1" and supports "EEDID version 1.3". 3. VEEDID power source shall be the limited current circuit which has not exceeding 1A. (Reference Document : "Enhanced Display Data Channel (E-DDCTM) Proposed Standard", VESA) 4. Both CLKEEDID line and DATAEEDID line are pulled up with 10k ohm resistor to VEEDID power source line at LCD panel, respectively. Voltage levels of all input signals are LVDS compatible (except VDD, EEDID). Refer to "Signal Electrical Characteristics for LVDS Receiver", for voltage levels of all input signals.
5.3 Interface Signal Description
Signal Description Signal Name RxIN0+, RxIN0RxIN1+, RxIN1RxIN2+, RxIN2RxCLKIN+, RxCLKINVDD GND Note :
O
Description LVDS differential data input (Red0-Red5, Green0) LVDS differential data input (Green1-Green5,Blue0-Blue1) LVDS differential data input (Blue2-Blue5, HSync, VSync, DSPTMG) LVDS differential clock input +3.3V Power Supply Ground
Input signals shall be low or Hi-Z state when VDD is off.
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Engineering Specification
SIGNAL NAME +RED5 +RED4 +RED3 +RED2 +RED1 +RED0
Description Red Data 5 (MSB) Red Data 4 Red Data 3 Red Data 2 Red Data 1 Red Data 0 (LSB) Red-pixel Data: Each red pixcel's brightness data consists of these 6 bits pixel data.
+GREEN 5 +GREEN 4 +GREEN 3 +GREEN 2 +GREEN 1 +GREEN 0
Green Data 5 (MSB) Green Data 4 Green Data 3 Green Data 2 Green Data 1 Green Data 0 (LSB) Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel data.
+BLUE 5 +BLUE 4 +BLUE 3 +BLUE 2 +BLUE 1 +BLUE 0
Blue Data 5 (MSB) Blue Data 4 Blue Data 3 Blue Data 2 Blue Data 1 Blue Data 0 (LSB) Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel data.
DTCLK +DSPTMG(DSP) VSYNC(V-S) HSYNC(H-S) VDD GND VEEDID CLKEDID DataEEDID
Data Clock:The typical frequency is 65.0 MHz. The signal is used to strobe the pixel data and the DSPTMG . When the signal is high, the pixel data shall be valid to be displayed. Vertical Sync:The signal is synchronized to DTCLK . Both active high/low signal acceptable. Horizontal Sync:The signal is synchronized with DTCLK . Both active high/low signals are acceptable. Power Supply Ground EEDID 3.3 V Power Supply EEDID Clock EEDID Data
Note : Output signals except VEEDID, CLKEEDID and DataEEDID from any system shall be Hi-Z state when VDD is off.
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Engineering Specification
5.3.1 E-EDID
E-EDID detail in this LCD module is in the following table. Address (hex) 00 - 07 08 - 09 0A - 0B 0C - 0F 10 11 12 - 13 14 - 18 Description Header ID Manufacturer Name ID Product Code ID Serial Number Week of Manufacture Year of Manufacture EDID Structure Version / Revision Basic Display Parameter / Features Color Characteristics Established Timing Standard Timing Identification Detailed Timing / Monitor Description #1 Detailed Timing / Monitor Description #2 Detailed Timing / Monitor Description #3 Detailed Timing / Monitor Description #4 Extension Flag Checksum Data (hex) 00 FF FF FF FF FF FF 00 24 94 0D 00 00 00 00 00 00 00 01 03 80 1E 17 78 0A Remark Header, Fixed "IDT" Product Code Unused Unused Unused Ver1.3 Active Area : 30.41cm x 22.81cm, Gamma : 2.2 Unused Unused
19 - 22 23 - 25 26 - 35
36 - 47
48 - 59 5A - 6B
(Note 1) 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 36 00 30 E4 10 00 00 18 (Note 1) 00 00 00 FE 00 49 44 54 0A 20 20 20 20 20 20 20 20 20 00 00 00 FE 00 4E 31 35 30 58 34 0A 20 20 20 20 20 20 00 (Note 1)
Typical Timing
Manufactuerer name "IDT" Manufacturer P/N "N150X4" No extension
6C - 7D
7E 7F
Note: 1.Detail data contents shall be determined with concurrence between user and International Display Technology(IDTech).
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Engineering Specification
5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
The LVDS receiver equipped in this LCD module is compatible with ANSI/TIA/TIA-644 standard. Electrical Characteristics Parameter Differential Input High Threshold Differential Input Low Threshold Magnitude Differential Input Voltage Common Mode Voltage Common Mode Voltage Offset Symbol Vth Vtl |Vid| Vcm Vcm -100 100 1.0 -50 1.2 600 1.5 +50 Min Typ Max +100 Unit mV mV mV V mV Vth - Vtl = 200mV Vth - Vtl = 200mV Conditions Vcm=+1.2V Vcm=+1.2V
Note : O Input signals shall be low or Hi-Z state when VDD is off. Voltage Definitions
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Engineering Specification
Measurement System
Timming Requirements Parameter Clock Frequency Cycle Time Data Setup Time (Note 1) Data Hold Time (Note 2) Cycle-to-cycle jitter (Note 3) Cycle Modulation Rate (Note 4) Symbol fc tc Tsu Thd tCCJ tCJavg Min 50 14.93 500 500 -150 +150 20 Typ 65 15.38 Max 67 20.00 Unit MHz ns ps ps ps fc = 65MHz, tCCJ < 50ps, Vth-Vtl = 400mV, Vcm = 1.2V, Vcm = 0 fc = 65MHz, Tsu=Thd=900ps Conditions
ps/clk fc = 65MHz, Tsu=Thd=900ps
Note : 1. All values are at VDD=3.3V, Ta=25 degree C. 2. See figure "Timing Definition" and "Timing Definition(detail A)" for definition. 3. Jitter is the magnitude of the change in input clock period. 4. This specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. Figure "Cycle Modulation Rate" illustrates a case against this requirement. This specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps.
(C) Copyright International Display Technology 2002 All Rights reserved. February 06,2003 OEM N150X4-L01-01 15/29
Engineering Specification
Timing Definition
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Engineering Specification
Timing Definition(detail A)
Note: Tsu and Thd are internal data sampling window of receiver. Trskm is the system skew margin; i.e., the sum of cable skew, source clock jitter, and other inter-symbol interference, shall be less than Trskm. Cycle Modulation Rate
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Engineering Specification
5.4.2 LVDS Receiver Internal Circuit
The following figure shows the internal block diagram of the LVDS receiver. This LCD module equips termination resistors for LVDS link.
5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection
Following the suggestions below will help to achieve optimal results. O Use controlled impedance media for LVDS signals. They should have a matched differential impedance of 100 ohm. O Match electrical lengths between traces to minimize signal skew. O Isolate TTL signals from LVDS signals. O For cables, twisted pair, twin, or flex circuit with close coupled differential traces are recommended.
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Engineering Specification
5.5 Signal for Lamp Connector
Pin # 1
2
Signal Name Lamp High Voltage Lamp Low Voltage
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Engineering Specification
6.0 Pixel format image
Following figure shows the relationship of the input signals and LCD pixel format image. Even and odd pair of RGB data are sampled at a time.
0 1st Line 1 1022 1023 RG B R G B
R GB R G B
768th Line RG B R G B
RG B R G B
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Engineering Specification
7.0 Parameter guide line for CFL Inverter
SYMBOL PARAMETER MIN D.P (Note 1) MAX UNITS CONDITION
(L63)
White Luminance (Center) CFL current CFL Peak Inrush Current CFL Frequency Inverter Ignition Voltage CFL Voltage (Reference) CFL Power consumption
3.0
215 6.5
7.0 20
[cd/m2] [mArms] [mA] [kHz] [Vrms]
Ta=25[deg. C] Ta=25[deg. C] (Note 2,5) Ta=25[deg. C] (Note 2,6) Ta=25[deg. C] (Note 3) Ta=0[deg. C] Ta=25[deg. C] Ta=25[deg. C] (Note 4)
ICFL ICFLP FCFL VCFLi VCFL PCFL
40 1,600 630 4.1
70
[Vrms] [W]
Note : 1. Design Point 2. If it exceeds MIN/MAX values, then"CFL Life" , "ON/OFF Cycle", and "SAFETY" will not be guaranteed. 3. CFL Frequency should be carefully determined to avoid interference between inverter and TFT LCD. 4. Calculated value for reference (ICFL x VCFL = PCFL). 5. It should be employed the inverter which has Duty Dimming, if ICFL is less than 4[mA]. 6. Duration: 50msec MAX
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Engineering Specification
The following chart is Luminance versus Lamp Current for your reference.
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Engineering Specification
8.0 Interface Timings
Basically, interface timings should match the VESA 1024x768 / 60 Hz (VG901101) manufacturing guide line timing. These timings described here are not actual input timings of LCD module but output timings of SN75LVDS86DGG(Texas Instruments) or equivalent.
8.1 Timing Characteristics
Symbol fdck tck tx tacx Hsync Hsw Hbp Hfp ty tacy Vsync Vw Vfp Vbp DTCLK Frequency DTCLK cycle time X total time X active time H frequency H-Sync width H back porch H front porch Y total time Y active time Frame rate V-sync Width V-sync front porch V-sync back porch 8 8 0 777 768 55 1 1 7 MIN 50.00 14.93 1206 1024 TYP 65.00 15.38 1344 1024 48.363 136 160 24 806 768 60 6 3 29 63 1023 768 61 510 MAX 67.00 20.00 2047 1024 Unit MHz nsec tck tck KHz tck tck tck tx tx Hz tx tx tx 1 2 2 Note
Note1 : Vbp should be static. Note2 : Hsw+Hbp> 32 [tck] - The timing interval between V-Sync falling edge and H-Sync rising edge should be fixed between each V-Frame.(V-Sync and H-Sync polarity are assumed to be positive in this case.)
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Engineering Specification
8.2 Timing Definition
1344 dot H-Sync 24 dot 160 dot
136 dot DSPTMG 1024 dot
V-Sync 3H 29H 6H DSPTMG 38H 768H
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Engineering Specification
9.0 Power Consumption
Input power specifications are as follows; SYMBOL VDD PDD PARAMETER Logic/LCD Drive Voltage VDD Power Min 3.0 Typ 3.3 1.6 (TBD) 2.2 (TBD) IDD VDD Current 490 (TBD) 640 (TBD) VDDrp Allowable Logic/LCD Drive Ripple Voltage 100 Max 3.6 UNITS [V] [W] [W] [mA] [mA] [mVp-p] CONDITION Load Capacitance 20[uF] All Black Pattern VDD=3.3[V] Max. Pattern, VDD=3.6[V] All Black Pattern, VDD=3.3[V] Max Pattern, VDD=3.0[V]
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Engineering Specification
10.0 Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from any system shall be Hi-Z state or low level when VDD is off.
30ms min.
VDD
10%
90%
90%
10%
10%
0V
0.1ms min. 30ms max.
0 min.
0 min.
Signals
10%
0V
10%
200ms min.
0 min.
Lamp On
10%
10%
0V
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Engineering Specification
11.0 Mechanical Characteristics
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Engineering Specification
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Engineering Specification
12.0 National Test Lab Requirement
The display module will satisfy all requirements for compliance to UL 60950, 3rd Edition CAN/CSA-C22.2 No. 60950-00 IEC 60950 (3rd. Ed.) EN 60950 (3rd. Ed.) U.S.A. Information Technology Equipment Canada, Information Technology Equipment International, Information Technology Equipment International, Information Technology Equipment (European Norm for IEC60950)
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